RTL Audio Lab

RTL Audio Lab https://validator.w3.org/feed/docs/rss2.html 028 – Standalone Simulation in Vivado (2) 037 – Scripting the FPGA Bitstream Programming in Vivado 034 – Fixed- vs. Floating-Point Processing in FPGAs 031 – Floating-Point FPGA Audio Limiter (3) 030 – Floating-Point FPGA Audio Limiter (2) 036 – Design Cleanup and Non-Project Mode (POTD 02) 029 – Floating-Point FPGA Audio Limiter (1) 027 – Standalone Simulation in Vivado (1) 035 – FPGA Floating-Point FIR Filter (2) 025 – Floating-Point FPGA Audio Equalizer (3) 024 – Floating-Point FPGA Audio Equalizer (2) 033 – FPGA Floating-Point FIR Filter (1) 032 – FPGA Audio Processor Block Design 023 – Floating-Point FPGA Audio Equalizer (1) 022 – Floating-Point Conversion Update (POTD 01) 021 – FPGA Audio Clipper 020 – RMS Metering with an FPGA 019 – Stereo LED Meter with Overflow Alarm 018 – FPGA Stereo Delay 017 – FPGA Mono Delay 015 – Setting up a gitignore File for Vivado Projects About 016 – Floating-Point Audio Processing with FPGAs 014 – Revision Control for Vivado Projects 013 – dBFS Conversion with Vitis HLS (4) 012 – dBFS Conversion with Vitis HLS (3) 011 – dBFS Conversion with Vitis HLS (2) 010 – dBFS Conversion with Vitis HLS (1) 009 – Reading WAVE Files in SystemVerilog 008 – FPGA Audio Monitor Controller 007 – FPGA Audio LED Meter 001 – ZedBoard Audio Processor 002 – ZedBoard Signal Debouncer 005 – FPGA Audio Processor Core 004 – ZedBoard Audio Codec SPI Controller 003 – ZedBoard Audio Codec Master Clock 026 – Happy New Year 2022! 006 – FPGA Audio (De)Serializer