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In this post, the first of a two-part series, we will explore how to set up and run an RTL simulation in Vivado that is separate from the synthesis and implementation flow.

In this non-technical post we will look back at 2021 and talk about what RTL Audio Lab has planned for 2022.

In this post, the final of a three-part series exploring an FPGA audio Equalizer based on a Biquad Filter, we will do a quick HLS implementation of our Biquad Equation module and compare its resource utilization and performance to our RTL description.

In this post, the second part of our series exploring a floating-point FPGA audio equalizer, we will describe the logic of our double-precision floating-point Biquad and use it implement a low-pass filter.

In this post we start a series wich will explore the implementation of an FPGA double-precision floating-point Biquad Filter as the basis for an Equalizer in our ZedBoard Audio Processor. In the first installment we will introduce the Biquad Filter, discuss the supporting modules required by our architecture and set up the simulation environment for…

In this post we introduce our Paying Off Technical Debt (POTD) recurring series, in which we revisit and make improvements to an existing element of our design. In the first installment we will update the fixed- to floating-point conversion in our Audio Processor.

In this post we will go over the implementation of a floating-point audio clipper for our FPGA Audio Processor.

In this post we will go over the implementation of an RMS meter on an FPGA.

In this post we will update our LED Meter to add support for stereo display and a visual overflow alarm.

In this post we will go over the implementation of a stereo delay effect for our FPGA Audio Processor.